Deadline
Varies
Value of Scholarship
Renewable
No
Application deadline: 15 December 2013
Start date: As soon as possible
Duration of award: 12 months
Funded by IVHM Centre, this studentship will cover the tuition fees at the UK/EU rate only and provide a bursary of up to £12,000 p.a for 1 year*
Supervisor:
Dr Suresh Perinpanayagam - suresh.nayagam@cranfield.ac.uk
Dr. Mohammad Samie - m.samie@cranfield.ac.uk
Overview:
This project aims to integrate power management solutions of highly-complicated electronic boards into commercial Field Programmable Gate Arrays (FPGAs). Providing power management facility for todayâs complex electronic systems is one of the main challenges that designers are facing to deliver highly-available and reliable systems. In such a complicated electronic board, there are various devices, often FPGAs, microcontrollers, microprocessors, ASICs, amongst others, assembled on the same board. To get all these devices (and thereby the whole electronic board) functional, additional care of power supplies, noise, temperature, amongst others, are required. Additionally, monitoring power consumption of devices provides key measurements of the devicesâ performance so that the degradation mechanisms and the remaining life time of the devices can be also calculated.
Basically, power management deals with the following items:
- Sequence of the power-up/down of various devices on the board (or complete system)
- Voltage monitoring and fault indicators
- Maintaining constant supply voltages by trimming output of the voltage regulators.
To improve reliability and availability of electronic systems, the basic power management unit should be boosted with new tasks and functionalities. The key role of the new functions is to evaluate the performance of systems by monitoring power supplies, power consumption, temperature, and noise.
The goal of this project is to examine each design step and component of system power with the purpose of providing techniques to measure availability and reliability of systems. These techniques cover system-partitioning, chip design, and board layout with Smart Fusion of Actel FPGA. The proposed design techniques cover RTL coding, arithmetic architecture power-profiling, and place-and-route hints. In addition, available power modes are exploited to minimize further power consumption, energy, and battery life.
Entry Requirements:
First-class or upper second-class degree in electronic or electrical engineering or a related area. Computer programming science and DSP background would be a distinct advantage as would experience of programming, signal processing, and modelling.
Funding:
*To be eligible for this funding, applicants must have:
- no restrictions on how long you can stay in the UK, i.e. no visa restrictions or have âsettled statusâ, and
- have been âordinarily residentâ in the UK for 3 years prior to the start of the grant and
- not been residing in the UK wholly or mainly for the purpose of full-time education. (This does not apply to UK or EU nationals).
All EU nationals are eligible to receive a fees-only award if they do not have âsettled statusâ in the UK.
All non-EU nationals are very unlikely to be eligible for this funding under the Education (Fees and Awards) Regulations 1997.
How to Apply:
For initial enquiries or for an informal discussion please emailÂ
Dr. Mohammad Samie -Â m.samie@cranfield.ac.uk
If you are eligible to apply for this research studentship, please complete the online application via the 'Apply' button below.
Please specify project title on the application form.
For further information contact us today:
School of Applied Sciences
T: +44 (0)1234 754086
E: appliedsciences@cranfield.ac.uk
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